Design and Characterization of a 5.2 GHz/2.4 GHz http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq1_HTML.gif Fractional- http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq2_HTML.gif Frequency Synthesizer for Low-Phase Noise Performance

  • John WM Rogers1Email author,

    Affiliated with

    • Foster F Dai2,

      Affiliated with

      • Calvin Plett1 and

        Affiliated with

        • MarkS Cavin3

          Affiliated with

          EURASIP Journal on Wireless Communications and Networking20062006:048489

          DOI: 10.1155/WCN/2006/48489

          Received: 8 August 2005

          Accepted: 13 January 2006

          Published: 15 March 2006

          Abstract

          This paper presents a complete noise analysis of a http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq3_HTML.gif -based fractional- http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq4_HTML.gif phase-locked loop (PLL) based frequency synthesizer. Rigorous analytical and empirical formulas have been given to model various phase noise sources and spurious components and to predict their impact on the overall synthesizer noise performance. These formulas have been applied to an integrated multiband WLAN frequency synthesizer RFIC to demonstrate noise minimization through judicious choice of loop parameters. Finally, predicted and measured phase jitter showed good agreement. For an LO frequency of 4.3 GHz, predicted and measured phase noise was http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq5_HTML.gif rms and http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq6_HTML.gif rms, respectively.

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          Authors’ Affiliations

          (1)
          Carleton University
          (2)
          Electrical and Computer Engineering Department, Auburn University
          (3)
          Alereon, Inc.

          References

          1. Riley TA, Copeland M, Kwasniewski T:Delta-sigma modulation in fractional- http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq7_HTML.gif frequency synthesis. IEEE Journal of Solid-State Circuits 1993,28(5):553-559. 10.1109/4.229400View Article
          2. Wells JN: Frequency Synthesizers. United States Patent, no. 4609881, September, 1986
          3. Miller B, Conley B: A multiple modulator fractional divider. Proceedings of the 44th Annual Symposium on Frequency Control, May 1990, Baltimore, Md, USA 559-568.View Article
          4. Muer B, Steyaert MSJ:A CMOS monolithic http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq8_HTML.gif -controlled fractional- http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq9_HTML.gif frequency synthesizer for DCS-1800. IEEE Journal of Solid-State Circuits 2002,37(7):835-844. 10.1109/JSSC.2002.1015680View Article
          5. Leeson DB: A simple model of feedback oscillator noise spectrum. Proceedings of IEEE 1966,54(2):329-330.View Article
          6. Rogers JWM, Plett C: Radio Frequency Integrated Circuit Design. Artech House, Norwood, Mass, USA; 2003.
          7. Watanabe Y, Okabayashi T, Goka S, Sekimoto H: Phase noise measurements in dual-mode SC-cut crystal oscillators. IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control 2000,47(2):374-378. 10.1109/58.827423View Article
          8. Kroupa VF: Jitter and phase noise in frequency dividers. IEEE Transactions on Instrumentation and Measurement 2001,50(5):1241-1243. 10.1109/19.963191View Article
          9. Kroupa VF: Noise properties of PLL systems. IEEE Transactions on Communications 1982,30(10):2244-2252. 10.1109/TCOM.1982.1095404View Article
          10. Egan WF: Frequency Synthesis by Phase Lock. John Wiley & Sons, New York, NY, USA; 2000.
          11. Rogers JWM, Dai FF, Cavin MS, Rahn DG:A multiband http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq10_HTML.gif fractional- http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq11_HTML.gif frequency synthesizer for a MIMO WLAN transceiver RFIC. IEEE Journal of Solid-State Circuits 2005,40(3):678-689.View Article
          12. Zargari M, Jen S, Kaczynski B, et al.: A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g WLAN. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '04), February 2004, San Francisco, Calif, USA 1: 96-515.
          13. Bouras J, Bouras S, Georgantas T, et al.:A digitally calibrated 5.15-5.825GHz transceiver for 802.11a wireless LANs in 0.18 http://static-content.springer.com/image/art%3A10.1155%2FWCN%2F2006%2F48489/MediaObjects/13638_2005_Article_1240_IEq12_HTML.gif m CMOS. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '03), February 2003, San Francisco, Calif, USA 1: 352-498.View Article
          14. Zhang P, Nguyen T, Lam C, et al.: A direct conversion CMOS transceiver for IEEE 802.11a WLANs. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '03), February 2003, San Francisco, Calif, USA 1: 354-498.View Article

          Copyright

          © John W. M. Rogers et al. 2006

          This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.